Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device is provided in which a lowering in the breakdown voltage of a gate insulating film (nitrided silicon oxide film) in a boundary region between the upper-end corner portion of the side wall of an element isolating groove and a silicon substrate in the end portion of an element forming region which is formed in contact therewith can be suppressed without causing an increase in the number of steps (time for effecting the steps). An element isolation insulating film is filled into the internal portion of the element isolating groove to cover the end portion of the silicon substrate in the element forming region which is formed in contact with the upper-end portion of the side wall of the element isolating groove, nitrogen is selectively doped into the surface of the silicon substrate in a region of the element forming region other than the end portion thereof with the element isolation insulating film used as a mask, then a portion of the element isolation insulating film lying outside the element isolating groove is removed to expose the upper-end portion of the side wall, and a nitrided silicon oxide film used as the gate insulating film is formed by the heat treatment in an atmosphere containing an oxidizing agent.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a semiconductor device using a siliconnitride film or silicon oxide film containing nitrogen as a gateinsulating film and a method for manufacturing the same.

[0002] In order to enhance the performance of a semiconductor integratedcircuit including MIS semiconductor elements and lower the cost thereof,it is important to miniaturize the elements and increase the integrationdensity. Miniaturization of the elements is effected according to thedesign rule.

[0003] Further, in order to increase the integration density of theelements, it is important to not only reduce the size of the elementsbut also reduce the size of the element isolating region. As theeffective technique for miniaturizing the size of the element isolatingregion, a trench type element isolation (STI: Shallow Trench Isolation)technique is known.

[0004] When a MOS transistor using a polysilicon film containing boronas a gate electrode is miniaturized, it is necessary to use a nitridedsilicon oxide film (which is a silicon oxide film containing nitrogen)as a gate insulating film in order to prevent boron from being diffusedinto the silicon substrate. It is necessary to simultaneously supply anoxidizing agent and nitriding agent in order to form a thinner nitridedsilicon oxide film.

[0005] Next, a method for manufacturing the MOS transistor using theabove gate insulating film (nitrided silicon oxide film) is explainedwith reference to FIGS. 9A to 9H. These figures show cross sections ofthe MOS transistor taken along a line passing across the gate electrodeand set in parallel to the gate length direction.

[0006] First, as shown in FIG. 9A, a silicon oxide film 82 with athickness of 10 nm is formed on the (100) surface of a silicon substrate81 by use of a thermal oxidation method. Then, as shown in FIG. 9A, asilicon nitride film 83 with a thickness of 200 nm is formed on thesilicon oxide film 82 by use of the LPCVD method.

[0007] Next, as shown in FIG. 9B, trench type shallow element isolationgrooves 84 are formed in the surface of the silicon substrate 81 bysequentially etching the silicon nitride film 83, silicon oxide film 82and silicon substrate 81.

[0008] In more detail, a photoresist pattern (not shown) which definesan element forming region (active area) is formed on the silicon nitridefilm 83 and the pattern of the photoresist pattern is transferred ontothe silicon nitride film 83 by etching the silicon nitride film 83 byuse of an RIE method with the photoresist pattern used as a mask.

[0009] Next, after the photoresist pattern is removed, the elementisolation grooves 84 are formed by sequentially etching the siliconoxide film 82 and the silicon substrate 81 by use of the RIE method withthe silicon nitride film 83 used as a mask.

[0010] After this, as shown in FIG. 9C, a silicon oxide film 85 with athickness of 15 nm is formed on the exposed surface of the siliconsubstrate 81 by use of a thermal oxidation method.

[0011] Next, as shown in FIG. 9D, an element isolation insulating film86 is filled in the internal portions of grooves formed by the elementisolation grooves 84 as well as the silicon nitride film 83 and siliconoxide film 82 lying thereon, and then the surface of the structure ismade flat.

[0012] In more detail, a silicon oxide fill used as the elementisolation insulating film 86 is formed on the entire surface by use ofthe LPCVD method so as to fill the grooves formed of the elementisolation grooves 84 and the silicon nitride film 83 lying thereon, thenthe silicon film is polished by use of the CMP method until the surfaceof the silicon nitride film 83 is exposed. As a result, the structure asshown in FIG. 9D is obtained.

[0013] Next, as shown in FIG. 9E, the element isolation insulating film(silicon oxide film) 86 is retreated to substantially the surfaceportion of the silicon substrate 81 by use of an ammonium fluoridesolution and the silicon nitride film 83 is removed by use of a hotphosphoric acid, then the silicon oxide film 82 is removed by use of adilute hydrofluoric acid to expose the surface of the silicon substrate81 (active area) in the element forming region.

[0014] Next, for example, as shown in FIG. 9F, an oxidizing-nitridingprocess is effected at 850° C. by use of dinitrogen monoxide gas, toform a nitrided silicon oxide film (gate insulating film) 87 with athickness of 4 nm on the exposed surface of the silicon substrate 81 andthen an amorphous silicon film 88 with a thickness of 100 nm, whichcontains boron as impurity with high impurity concentration and whichwill be used as a gate electrode, is formed by use of the LPCVD method.

[0015] After this, like a conventional MOS transistor manufacturingmethod, the processes for patterning the gate electrode, for formingsource and drain diffusion layers and for forming wirings are effectedto complete a MOS transistor.

[0016] However, this type of MOS transistor manufacturing method has thefollowing problem.

[0017] As shown in FIGS. 9G, the portion of the nitrided silicon oxidefilm (gate insulating film) 87 lying on the upper-end corner portion ofthe side wall of the element isolation groove 84 is not so thick as theportion of the same lying on the element forming region. Therefore, thebreakdown voltage of the nitrided silicon oxide film (gate insulatingfilm) 87 on the upper-end corner portion of the side wall of the elementisolation groove 84 in which the electric field is concentrated becomeslow and thus the reliability is lowered.

[0018] Further, in the thermal oxidation method, which is a conventionalmethod for forming a normal gate insulating film, the oxidation ratevaries on the (100) face and the (110) face which correspond to the sidewall surface of the element isolating groove 84, (the rate on the (110)face is about 1.5 times greater than that on the (100) face) andtherefore, as shown in FIG. 9H, the film thickness of the thermalsilicon oxide film (gate insulating film) 87 at the upper-end cornerportion of the side wall of the element isolation groove 84 is greaterthan the film thickness of the thermal silicon oxide film (gateinsulating film) 87 in the element forming region. A high breakdownvoltage of the thermal silicon oxide film (gate insulating film) 87 istherefore attained and thus there have been no problems regarding a lowreliability due to a low gate breakdown voltage. However, if adinitrogen monoxide gas is employed, both oxidation and nitration mayoccur, and thus the difference of oxidation rate on the (100) face andthe (110) face may be reduced.

[0019] In order to solve the problem of a lowering in the breakdownvoltage of the nitrided silicon oxide film (gate insulating film) 87, aportion of the nitrided silicon oxide film (gate insulating film) 87 atthe above-mentioned corner portion, that is, a portion lying between theupper-end corner portion of the side wall of the element isolationgroove 84 and the end portion of the element forming region formed incontact therewith may be made thicker than a portion of the nitridedsilicon oxide film (gate insulating film) 87 which lies on the centralflat portion of the element forming region.

[0020] Such a technique for forming a gate insulating film havingdifferent film thickness on different regions of the substrate is knownin the prior art (refer to Japanese Patent Application No. 3-249810).

[0021] However, if this type of conventional technique is used, it willbe necessary to use the photolithography in order to mask the cornerportion, and therefore, additional steps (additional time for effectingthe steps) and additional manufacturing costs will be necessary.

[0022] Further, a problem of misalignment may occur and it is thereforedifficult to form a thick gate insulating film oil the corner portionwithout fault.

[0023] As described above, in a MOS transistor using the nitridedsilicon oxide film as the gate insulating film, it has been consideredthat a nitrided silicon oxide film is formed so as to have a thin parton the central flat portion of the element forming region as designedand a thick part on the corner portion, to prevent a lowering in thebreakdown voltage of the gate insulating film in the corner portion.

[0024] However, such a conventional method for forming the gateinsulating film having different film thickness on the different regionsof the substrate requires the photolithography.

[0025] Therefore, there occur problems that additional steps (additionaltime for effecting the steps) as well as additional manufacturing costswill be needed and it is difficult to form a thick gate insulating filmon the corner portion without fault, due to misalignment.

BRIEF SUMMARY OF THE INVENTION

[0026] This invention has been achieved in consideration of the aboveproblems. An object of the present invention is to provide asemiconductor device having a gate insulating film which is formed of asilicon nitride film or silicon oxide film containing nitrogen, which isformed in a self-alignment manner, and which can prevent deteriorationof the breakdown voltage in a boundary region defined between an elementforming region and an element isolating region, and to provide a methodfor manufacturing the same.

[0027] According to the first aspect of the present invention, there isprovided a semiconductor device comprising a silicon substrate includingan element forming region, an element isolating region, and a boundaryregion defined between the element forming region and the elementisolating region, including the boundary between the element formingregion and the element isolating region, and a gate insulating filmformed on the surface of the silicon substrate to extend from theelement forming region to the element isolating region across theboundary region, wherein the gate insulating film includes either of asilicon nitride film or a silicon oxide film containing nitrogen and isformed in a self-alignment manner to make the thickness of the gateinsulating film on the boundary region greater than the thickness of thegate insulating film in the regions other than the boundary region.

[0028] According to the second aspect of the present invention, there isprovided a method for manufacturing a semiconductor device, comprisingthe steps of dividing the silicon substrate into the element formingregion and the element isolating region, doping nitrogen into thesurface of the silicon substrate in the element forming region, andforming the gate insulating film on the surface of the silicon substrateso that the gate insulating film can extend from the element formingregion to the element isolating region across the boundary region, bythe heat treatment in an atmosphere containing an oxidizing agent.

[0029] According to the third aspect of the present invention, there isprovided a method for manufacturing the semiconductor device, comprisingthe steps of dividing a silicon substrate into an element forming regionand an element isolating region, doping nitrogen into the surface of thesilicon substrate in the boundary region, and forming a silicon nitridefilm or a silicon oxide film containing nitrogen as the gate insulatingfilm so that the gate insulating film can extend on the surface of thesilicon substrate from the element forming region to the elementisolating region across the boundary region.

[0030] According to the fourth aspect of the present invention, there isprovided a method for manufacturing the semiconductor device, whereinthe silicon substrate is a crystalline silicon substrate, and the methodcomprises the steps of dividing the crystalline silicon substrate intoan element forming region and an element isolating region, selectivelyforming the surface of the silicon substrate in the boundary region intoan amorphous form, and forming the silicon nitride film or the siliconoxide film containing nitrogen as the gate insulating film by use of anitriding method, so that the gate insulating film can extend from theelement forming region to the element isolating region across theboundary region.

[0031] It is preferable to use an insulating film of a laminatedstructure including a silicon nitride film as the gate insulating film.

[0032] In the methods for manufacturing the semiconductor deviceaccording to this invention, it is preferable to perform the step ofdoping nitrogen into the surface of the silicon substrate by use of, forexample, a thermal nitriding method using nitriding agent gas such asnitrogen monoxide gas or ammonium gas, a radical nitriding method usingactive nitrogen atoms, or an ion implantation method using nitrogen ion.

[0033] Further, in the methods for manufacturing the semiconductordevice according to this invention, it is preferable to form achemically grown film on a region other than the boundary region of theelement forming region before the gate insulating film is formed by useof the nitriding method.

[0034] Further, in the methods for manufacturing the semiconductordevice according to this invention, it is preferable to use ion of aninert element such as helium, neon, argon, krypton or xenon, nitrogenion, oxygen ion or silicon ion as the ion implanted into the surface ofthe silicon substrate.

[0035] According to this invention, in the semiconductor device usingthe silicon nitride film or silicon oxide film containing nitrogen asthe gate insulating film, since the film thickness of the gateinsulating film in the boundary region defined between the elementforming region and the element isolating region is greater than the filmthickness of the gate insulating film in the element forming region, alowering in the breakdown voltage in the boundary region can besuppressed.

[0036] Further, since the gate insulating film can be formed in theself-alignment manner by the manufacturing method of this invention, thenumber of steps (time for effecting the steps) and the manufacturingcost can be reduced and the film of a sufficient thickness in theboundary region can be stably provided.

[0037] According to this invention, since nitrogen is doped into thesurface of the silicon substrate in which the film thickness is madesmall and nitrogen is not doped into the surface of the siliconsubstrate in which the film thickness is made large, the gate insulatingfilm (silicon oxide film containing nitrogen, silicon nitride film)having different film thickness can be formed in a self-alignment mannerby the heat treatment in an atmosphere containing an oxidizing agent.

[0038] Further, according to this invention, since nitrogen is not dopedinto the surface of the silicon substrate in which the film thickness issmall and nitrogen is doped into the surface of the silicon substrate inwhich the film thickness is large, the gate insulating film (siliconoxide film containing nitrogen, silicon nitride film) having differentfilm thickness can be formed in a self-alignment manner by use of thedeposition method.

[0039] Further, according to this invention, in the area where nitrogenis not doped into the surface of the silicon substrate, the filmthickness is made small while in the area where nitrogen is doped intothe surface of the silicon substrate, the film thickness is made large.Hence, the gate insulating film (silicon oxide film containing nitrogen,silicon nitride film) having different film thickness can be formed in aself-alignment manner by use of the nitriding method.

[0040] Further, according to this invention, since the surface of thesilicon substrate in which tale film thickness is made small is kept inthe single crystal form and the surface of the silicon substrate inwhich the film thickness is made large is formed into the amorphousform, the gate insulating film (silicon oxide film containing nitrogen,silicon nitride film) having different film thickness can be formed in aself-alignment manner by use of the nitriding method.

[0041] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0042] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrated presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0043]FIGS. 1A to 1J are cross sectional views showing the steps of amethod for manufacturing a MOS transistor according to the firstembodiment of this invention;

[0044]FIG. 2 is a graph showing curves of oxide thickness for oxidationtime in a case where nitrogen is implanted and a case where nitrogen isnot implanted;

[0045]FIGS. 3A to 3F are cross sectional views showing the steps of amethod for manufacturing a MOS transistor by using an embodiment of thepresent invention in combination with a damascene gate method;

[0046]FIGS. 4A to 4G are cross sectional views showing the steps of amethod for Manufacturing a MOS transistor according to the secondembodiment of this invention;

[0047]FIG. 5 is a graph showing the relationships of deposition time andsilicon nitride film thickness in a case where nitridation is performedand in a case where nitridation is not performed;

[0048]FIGS. 6A to 6C are cross sectional views showing the steps of amethod for manufacturing a MOS transistor according to the thirdembodiment of this invention;

[0049]FIGS. 7A to 7G are cross sectional views showing the steps of themethod for manufacturing the MOS transistor according to the fourthembodiment of this invention;

[0050]FIG. 8 is a cross sectional view for illustrating a modificationof this invention; and

[0051]FIGS. 9A to 9H are cross sectional views showing the steps of amethod for manufacturing a conventional MOS transistor.

DETAILED DESCRIPTION OF THE INVENTION

[0052] There will now be described embodiments of this invention withreference to the accompanying drawings.

First Embodiment

[0053]FIGS. 1A to 1J are cross sectional views showing the steps of amethod for manufacturing a MOS transistor according to a firstembodiment of this invention. Those figures show cross sections takenalong a line passing across the gate electrode and set in parallel tothe gate length direction.

[0054] First, as shown in FIG. 1A, a silicon oxide film 2 with athickness 10 nm is formed on the (100) surface of a single crystalsilicon substrate 1 by use of a thermal oxidizing method. Then, as shownin FIG. 1A, a silicon nitride film 3 of 200 nm thickness is formed onthe silicon oxide film 2 by use of an LPCVD method.

[0055] Next, as shown in FIG. 1B, trench type shallow element isolatinggrooves 4 are formed in the surface of the silicon substrate 1 bysequentially etching the silicon nitride film 3, silicon oxide film 2and silicon substrate 1.

[0056] In more detail, a photoresist pattern (not shown) which definesan element forming region (active area) is formed on the silicon nitridefilm 3 and the pattern of the photoresist pattern is transferred ontothe silicon nitride film 3 by etching the silicon nitride film 3 by useof an RIE method with the photoresist pattern used as a mask.

[0057] Next, after the photoresist pattern is removed, the elementisolating grooves 4 are formed by sequentially etching the silicon oxidefilm 2 and silicon substrate 1 by use of the RIE method with the siliconnitride film 3 used as a mask.

[0058] After this, as shown in FIG. 1C, the exposed surface of thesilicon nitride film 3 is retreated by 20 nm by use of a hot phosphoricacid.

[0059] Next, as shown in FIG. 1D, a silicon oxide film 5 with athickness of 15 nm is formed on the surface of a portion of the siliconsubstrate 1 which is not covered with the silicon nitride film 3 by useof a thermal oxidation method.

[0060] Then, as shown in FIG. 1E, an element isolation insulating film 6is filled in the internal portions of grooves formed of the elementisolation grooves 4 and the silicon nitride film 3 and silicon oxidefilm 2 lying thereon, Then, the surface of the structure is made flat.

[0061] In more detail, after a silicon oxide film with a thickness of500 nm used as the element isolation insulating film 6 is formed on theentire surface by use of the LPCVD method to fill the internal portionsof the grooves formed of the element isolation grooves 4 and the siliconnitride film 3 and the like lying thereon, the structure as shown inFIG. 1E is provided by polishing the silicon film by use of the CMPmethod until the surface of the silicon nitride film 3 is exposed.

[0062] Next, as shown in FIG. 1F, after the surface of the elementisolation insulating film (silicon oxide film) 6 is retreated by use ofan ammonium fluoride solution, the silicon nitride film 3 is removed byuse of a hot phosphoric acid.

[0063] Next, as shown in FIG. 1G, nitrogen is doped into the surface ofthe central flat portion of the silicon substrate 1 in the elementforming region, from which the silicon nitride film 3 has been removed,by use of the ion-implantation technique using nitrogen ion. In FIG. 1G,a reference numeral 7 indicates a region in which nitrogen is doped(nitrogen doped region).

[0064] Introduction of nitrogen may be implemented by use of the thermalnitriding method using nitriding agent gas such as NH₃ gas, N₂O gas, NOgas or, by use of the radical nitriding method employing a nitrogenradical, for example.

[0065] Those nitrogen introduction methods make it possible to dopenitrogen into the surface of the silicon substrate 1 even in the casewhere the surface of the silicon substrate 1 is covered with the siliconoxide film 2.

[0066] Particularly, when the radical nitriding method is used,introduction of nitrogen can be effected even at low temperatures, forinstance in the range between a room temperature and 700C°, so thatoccurrence of a variation in the impurity profile in the channel regioncan be prevented and a fluctuation in the threshold voltage can beprevented.

[0067] When the ion implantation technique (the acceleration voltageused therefor may be, for example, in the range between 5 KeV and 10KeV) is used, nitrogen introduction with higher concentration can beachieved. As a result, a gate insulating film having a larger differencein the film thickness can be provided in the next step as shown in FIG.1I. In this step, it is preferable to make the concentration of nitrogenlower than 10¹⁵ cm⁻², in consideration of affects to the crystalstructure of the silicon substrate.

[0068] Next, as shown in FIG. 1H, a portion of the silicon substrate 1in the element forming region and a portion of the silicon substrate 1in the boundary region corresponding to the upper-end corner portion ofthe element isolating groove 4 are exposed by retreating the surface ofthe element isolation insulating film (silicon oxide film) 6 tosubstantially the same height of the surface of the silicon substrateand removing the silicon oxide film 2 by use of a dilute hydrofluoricacid.

[0069] Next, as shown in FIG. 1I, a nitrided silicon oxide film (gateinsulating film) 8 is formed on the surface of the silicon substrate 1by effecting an oxidizing-nitriding process at 850° C. by use ofdinitrogen monoxide gas, for example.

[0070] Since the growth rate of an oxide film on an area of siliconsubstrate surface where nitrogen is doped is different from that of anarea where nitrogen is not doped, there will be a thickness differencebetween those two areas. FIG. 2 shows, as an example, the relationbetween the oxidation time and the thickness of an oxide film formed onthe (100) face in the case where nitrogen is implanted, and that in thecase where nitrogen is not implanted. In this example, the process isconducted with a nitrogen ion dose amount of 2×10¹⁴ cm⁻² at atemperature of 850C°. According to the example of this figure, assumingthat the oxidation time is 30 minutes, the oxides film on the area wherenitrogen has been implanted will be about 4 nm in thickness, while thaton the area where nitrogen is not implanted will be 6 nm in thickness.

[0071] That is, if the oxide film is provided under the condition asmentioned above, the nitrided silicon oxide film (gate insulating film)8 of 4 nm thickness will be formed on the central flat portion of thesilicon substrate 1 in the element forming region, while the nitridedsilicon oxide film (gate insulating film) 8 with a larger thickness of 6nm will be provided in the boundary region including the upper-endcorner portion of the side wall of the element isolating groove 4 andthe end portion (a region in which nitrogen is not doped) of the elementforming region formed in contact therewith, as shown in FIG. 1J.

[0072] If the heat treatment is carried out in an oxidizing gasatmosphere containing nitrogen such as a dinitrogen monoxide gas,instead of a dry oxygen, it is possible to form the gate insulating film8 in a manner such that the thickness thereof on the corner portionwhere no nitrogen is doped is greater than that on a portion wherenitrogen is doped, and therefore, the gate insulating film 8 containingnitrogen can be formed on the corner portion by effecting the heattreatment in an oxidizing gas atmosphere containing nitrogen as in thisembodiment. Hence, the penetrationpenetration of boron can be furthereffectively prevented.

[0073] That is, according to this embodiment of the invention, thenitrided silicon oxide film (gate insulating film) 8, the thickness ofwhich at the corner portion is greater than that at the central flatportion in the element forming region can be formed in a self-alignmentmanner.

[0074] Therefore, the number of steps (time for effecting the steps) andthe manufacturing cost can be reduced and a gate insulating film havinga sufficient thickness in the boundary region can be stably provided.

[0075] Further, concentration of the electric field in the nitridedsilicon oxide film (gate insulating film) 8 at the corner portion can bealleviated and the reliability of the nitrided silicon oxide film (gateinsulating film) 8 is enhanced.

[0076] The stress applied on the nitrided silicon oxide film (gateinsulating film) 8 lying near the interface with the silicon substrate 1is reduced and the reliability is enhanced.

[0077] Next, as shown in FIG. 1I, an amorphous silicon film 9 with athickness of 100 nm which contains boron as impurity with high impurityconcentration and which will be used as a gate electrode is formed byuse of the LPCVD method.

[0078] Note that the nitrogen contained in the nitrided silicon oxidefilm (gate insulating film) 8 will prevent the boron in the amorphoussilicon film (gate electrode) 9 from diffusing into the siliconsubstrate 1, and as a result, a high-speed MOS transistor can beprovided according to the original design.

[0079] Further, since nitrogen is contained in the nitrided siliconoxide film (gate insulating film) 8, the film thickness of the nitridedsilicon oxide film (gate insulating film) 8 expressed in terms of thefilm thickness of the silicon oxide film is made smaller than thephysical film thickness of the nitrided silicon oxide film (gateinsulating film) 8.

[0080] Therefore, even if the physical film thickness of the nitridedsilicon oxide film (gate insulating film) 8 is made larger in order toenhance the reliability in the central flat portion of the siliconsubstrate 1 in the element forming region, it is still possible toprovide a high-speed MOS transistor by using the present invention.

[0081] After this, like the normal MOS transistor manufacturing method,the processes for patterning the gate electrode, forming source anddrain diffusion layers and forming wirings are effected to complete theMOS transistor.

[0082] This embodiment of the invention will be more advantageous if adamascene gate method (IEDM Tech (1998) pp 785) is used in combinationwith this embodiment for manufacturing a semiconductor device. In a casewhere the present invention and a damascene gate method are combined,the process for manufacturing a MOS transistor will be carried out inthe following manner:

[0083] Firstly, the steps as shown in FIGS. 1A to 1H are done. Note thatthe element isolating film 6 is partially scooped away at the portionsin contact with both side surfaces of the element forming region whenthe step shown in FIG. 1H is performed.

[0084] Next, wiring for gate electrodes is prepared by using a damascenegate method. The following process will be explained with reference toFIGS. 3A to 3F. FIGS. 3A, 3C, and 3C are cross sectional views of theMOS transistor taken along a line passing across the gate electrode andset in parallel to the gate length direction. FIGS. 3B, 3D, and 3E arecross sectional views taken along line I-I in FIG. 3A, line II-II inFIG. 3C, and line III-III in FIG. 3E, respectively.

[0085] Firstly, as shown in FIGS. 3A and 3B, dummy gate pattern 11,whichis a silicon oxide film formed by an LPCVD method, is provided on theelement forming region and on the element isolating region, with thesilicon oxide film 15 formed by an LPCDV method being interposed. Thedummy gate pattern 11 may be of laminated structure. In this embodiment,a laminated structure consisting of a silicon nitride layer 16 and anamorphous silicon layer 17 is used as the dummy gate pattern 11.

[0086] Next, after source/drain regions 12 are formed, silicon nitridefilm 13 is provided on the dummy gate pattern 11 and the surface of thesource/drain regions. Further, an insulating film 14 is formed on thesilicon nitride film 13 so as to have substantially the same height asdummy gate pattern 11, as shown in FIGS. 3C and 3D.

[0087] Next, insulating film 14 and silicon nitride film 13 are removedby using a CMP method, so that the top of the dummy gate pattern 11 maybe exposed. Then, the dummy gate pattern 11 and the silicon oxide film15 are removed by etching, as shown in FIGS. 3E and 3F.

[0088] As is seen from FIG. 3E, due to the etching effect to remove thesilicon oxide film 15, the element insulating film 6 has been furtherdeeply scooped away at the portions contacting the side surfaces ofelement forming region, in comparison with the state when the process ofFIG. 1H has been performed.

[0089] In the above step, the portions of element insulating film 6 in aboundary region including the boundary between the element formingregion and the element isolating region has been further deeply scooped.Thus, if a gate insulating film is formed thereon, the film 6 willsteeply be curved in the boundary region, with the result that a heavyelectric field concentration may be caused at the steeply curvedportion.

[0090] Under the above condition, the embodiment of the presentinvention enables formation of a gate insulating film having a suitablethickness in the boundary region in a self-alignment manner, so thatthere can be provided a gate insulating film that can withstand a heavyelectric field concentration and that is a high reliability.

[0091] As described above, according to this embodiment, after nitrogenis selectively doped into the central flat portion of the siliconsubstrate 1 in the element forming region, the gate insulating film 8having a large film thickness in the corner portion can be formed in aself-alignment manner by effecting the heat treatment in an atmospherecontaining an oxidizing agent, and as a result, an increase in thenumber of steps (time for effecting the steps) can be suppressed. Inaddition, in a case that the present invention is used in combinationwith a damascene gate method, there can be provided a MOS transistorwith a high reliability.

Second Embodiment

[0092]FIGS. 4A to 4G are cross sectional views showing the steps of amethod for manufacturing a MOS transistor according to a secondembodiment of this invention. Those figures show cross sections takenalong a line passing across the gate electrode and set in parallel tothe gate length direction. Further, portions which correspond to thoseshown in FIGS. 1A to 1J are denoted by the same reference numerals as inFIGS. 1A to 1J and therefore a detail explanation thereof is omittedherein.

[0093] First, after the process from the step of FIG. 1A to the step ofFIG. 1D in the above first embodiment is effected, nitrogen is dopedinto the surface of a portion of a silicon substrate 1 which is coveredwith a silicon oxide film 5, by using the thermal nitriding method withNH₃ gas, as shown in FIGS. 4A and 4B. In FIG. 4B, a reference numeral 7a indicates the region in which nitrogen is doped (nitrogen dopedregion).

[0094] Like the first embodiment, doping of nitrogen may be implementedby using the thermal nitriding method with N₂O gas, NO gas or the like,the radical nitriding method with a nitrogen radical, or the ionintroduction technique with a nitrogen ion.

[0095] Next, as shown in FIG. 4C, an element isolating film (siliconoxide film) 6 is filled in the internal portions of grooves formed ofelement isolating grooves 4 and a silicon nitride film 3 and siliconoxide film 2 lying thereon so as to make the surface of the structureflat.

[0096] Then, as shown in FIG. 4D, after the surface of the elementisolation insulating film (silicon oxide film) 6 is retreated by use ofan ammonium fluoride solution and the silicon nitride film 3 is removedby use of a hot phosphoric acid.

[0097] Next, as shown in FIG. 4E, a portion of the silicon substrate 1in the element forming region and a portion of the silicon substrate 1corresponding to the upper-end corner portion of the element isolatinggroove 4 are exposed by retreating the surface of the element isolationinsulating film (silicon oxide film) 6 substantially to the surface ofthe silicon substrate and removing the silicon oxide film 2 by use of adilute hydrofluoric acid.

[0098] Next, as shown in FIG. 4F, a silicon nitride film (gateinsulating film) 8 is formed on the surface of the silicon substrate 1by the LPCVD method using mixed gas of NH₃ and SiH₂Cl₂.

[0099] In this case, if the silicon nitride film (gate insulating film)8 a is formed by deposition with an LPCVD method in a manner such thatthe thickness is 8 nm at the central flat portion (nitrogen doped region7 a) of the silicon substrate 1 in the element forming region, thesilicon nitride film (gate insulating film) 8 will have a greaterthickness of 10 nm at the corner portion defined between the upper-endcorner portion of the side wall of the element isolating groove 4 andthe end portion (a region in which nitrogen is not doped) of the elementforming region formed in contact therewith as shown in FIG. 4G.

[0100] The reason why the film becomes thicker at the corner portion isthat nitrogen is doped in the corner portion and the reaction time ofthe initial period of deposition is thus short. FIG. 5 shows therelations between a silicon nitride film thickness and a deposition timein a case where nitrogen is doped in the substrate, and in a case whereit is not doped. According to this, a silicon nitride film growsimmediately when a deposition is started in a case where nitrogen isdoped, while it takes about 5 minutes before a silicon nitride filmstart to grow in a case where nitrogen is not doped. This time delay offilm deposition will provide a difference in the thickness of thesilicon nitride film.

[0101] That is, according to this embodiment, the silicon nitride film(gate insulating film) 8 a whose film thickness is larger on the surfaceof the silicon substrate 1 in the corner portion than on the surface ofthe central flat portion of the silicon substrate 1 in the elementforming region can be formed in a self-alignment manner.

[0102] Next, as shown in FIG. 4F, an amorphous silicon film 9 with athickness of 100 nm which contains boron as impurity with high impurityconcentration and which will be used as a gate electrode is formed byuse of the LPCVD method.

[0103] After this, like the normal MOS transistor manufacturing method,the processes for patterning the gate electrode, forming source anddrain diffusion layers and forming wirings are effected to complete theMOS transistor.

[0104] As described above, according to this embodiment, after nitrogenis selectively doped into the corner portion without doping nitrogeninto the central flat portion of the silicon substrate 1 in the elementforming region, the silicon nitride film (gate insulating film) 8 ahaving a large film thickness on the corner portion can be formed in aself-alignment manner by depositing silicon nitride, and as a result, anincrease in the number of steps (time for effecting the steps) can besuppressed. In addition, the same effect as that in the first embodimentcan be attained.

[0105] In this embodiment, the silicon nitride film is used as the gateinsulating film and the doped amorphous silicon film is used as the gateelectrode, but even if an insulating film of laminated structureincluding a silicon nitride film (lower layer) and a Ta₂O₅ film (upperlayer) is used as the gate insulating film and an Ru film is used as thegate electrode, the breakdown voltage of the gate insulating film in thecorner portion can be enhanced since the silicon nitride film formed asthe lower layer is made thick in the corner portion.

Third Embodiment

[0106]FIGS. 6A to 6C are cross sectional views showing the steps of amethod for manufacturing a MOS transistor according to a thirdembodiment of this invention. Those figures show cross sections takenalong a line passing across the gate electrode and set in parallel tothe gate length direction. Further, portions which correspond to thoseof FIGS. 4E to 4G are denoted by the same reference numerals as in FIGS.4E to 4G, and therefore a detail explanation thereof is omitted herein.

[0107] First, after the process up to the step of FIG. 4E in the secondembodiment is effected (FIG. 6A), an underlying silicon nitride film(not shown) is formed on the surface of a silicon substrate 1 by thenitriding method with a nitrogen radical, NH₃ gas or NO gas, forexample, as shown in FIG. 6B, and then a silicon nitride film (gateinsulating film) 8 a with a thickness of 4 nm is formed on theunderlying silicon nitride film by use of the LPCVD method with a mixedgas of NH₃ and SiH₂Cl₂.

[0108] If the underlying silicon nitride film is formed in a manner suchthat the thickness thereof at the central flat portion of the siliconsubstrate 1 in the element forming region is approx. 1 nm, theunderlying silicon nitride film with a thickness of 2 nm is formed onthe corner portion which is a portion lying between the upper-end cornerportion of the side wall of an element isolation groove 4 and the endportion of the element forming region formed in contact therewith. Thereason why the film thickness at the corner portion becomes larger isthat a nitrogen doped region 7 a has been formed on this portion.

[0109] Therefore, as shown in FIG. 6C, the total thickness (5 nm) of theunderlying silicon nitride film (1 nm) and the gate insulating film(silicon nitride film) 8 a (4 nm) at the central flat portion of thesilicon substrate 1 in the element forming region is smaller than thetotal thickness (6 nm) of the underlying silicon nitride film (2 nm) andthe gate insulating film (silicon nitride film) 8 a (4 nm) on the cornerportion on the silicon substrate 1.

[0110] That is, according to this embodiment, the gate insulating film(silicon nitride film 8 a+underlying silicon nitride film) of which thefilm thickness on the corner portion is larger than that at the centralflat portion of the silicon substrate 1 in the element forming regioncan be formed in a self-alignment manner.

[0111] Next, as shown in FIG. 6B, an amorphous silicon film 9 with athickness of 100 nm which contains boron as impurity with high impurityconcentration and which will be used as a gate electrode is formed byuse of a LPCVD method.

[0112] After this, similar to the normal MOS transistor manufacturingprocess, the processes for patterning the gate electrode, forming sourceand drain diffusion layers and forming wirings are effected to completethe MOS transistor.

[0113] As described above, according to this embodiment, after nitrogenis selectively doped into the corner portion without doping nitrogeninto the central flat portion of the silicon substrate 1 in the elementforming region, the silicon nitride film (gate insulating film) 8 ahaving a large film thickness at the corner portion can be formed in aself-alignment manner by nitriding the surface of the silicon substrate1, and as a result, an increase in the number of steps (time foreffecting the steps) can be prevented. In addition, the same effect asthat of the first embodiment can also be attained.

[0114] If the silicon oxide film 2 is removed after the step of FIG. 3Dand then the nitriding process for forming the underlying siliconnitride film is effected after a chemically grown film is formed on thesurface of the silicon substrate 1 in the element forming region, therecan be provided an underlying silicon nitride film having a largerdifference between the film thickness at the corner portion and the filmthickness at the central flat portion of the element forming region dueto suppression of nitration by the presence of the chemically grownfilm, and the effect that the fixed charge density in the underlyingsilicon nitride film formed is reduced can be attained.

[0115] Further, this embodiment uses the silicon nitride film 8 a as thegate insulating film formed by the deposition method, and also uses thedoped amorphous silicon film as the gate electrode, but a Ta₂O₅ film orBSTO film formed by the deposition method may be used as the gateinsulating film, and an Ru film may be used as the gate electrode, forexample. In a case where they are used, the breakdown voltage of thegate insulating film in the corner portion can be enhanced since theunderlying silicon nitride film is made thick at the corner portion.Further, a silicon nitride film of single layer structure formed bynitriding the surface of the silicon substrate may be used as the gateinsulating film.

Fourth Embodiment

[0116]FIGS. 7A to 7G are cross sectional views showing the steps of amethod for manufacturing a MOS transistor according to the fourthembodiment of this invention. Those figures show cross sections takenalong a line passing across the gate electrode and set in parallel tothe gate length direction. Further, portions which correspond to thoseof FIGS. 1A to 1G are denoted by the same reference numerals as in FIGS.1 and 2, and therefore a detail explanation thereof is omitted herein.

[0117] First, after the process from the step of FIG. 1A to the step ofFIG. 1D in the first embodiment is effected (FIG. 7A), ion of an elementsuch as silicon, helium, neon, argon, krypton, xenon, nitrogen or oxygenis doped into the surface of a portion of the silicon substrate 1 whichis covered with a silicon oxide film 5 to make the surface into anamorphous form. In FIG. 7B, reference numeral 10 indicates a siliconregion (amorphous silicon region) which is made into the amorphous form.

[0118] It silicon, which is the same as the constituent element of thesilicon substrate 1, is selected as a doped element, the devicecharacteristic is not influenced since reaction of the doped element(silicon) and the silicon substrate 1 does not occur.

[0119] Next, as shown in FIG. 7C, an element isolation insulating film(silicon oxide film) 6 is filled into grooves formed of the elementisolation grooves 4 and the silicon nitride film 3 and silicon oxidefilm 2 lying thereon, and then the surface of the structure is madeflat.

[0120] Next, as shown in FIG. 7D, the surface of the element isolationinsulating film (silicon oxide film) 6 is retreated by use of anammonium fluoride solution, and then the silicon nitride film 3 isremoved by use of a hot phosphoric acid.

[0121] Next, as shown in FIG. 7E, the surface of the element isolatingfilm (silicon oxide film) 6 is retreated substantially to the surface ofthe substrate, and the silicon oxide film 2 is removed by use of adilute hydrofluoric acid to expose a portion of the silicon substrate 1in the element forming region and a portion of the silicon substrate 1in the boundary region including the upper-end corner portion of theside wall of the element isolating groove 4.

[0122] In this case, the process from the step of forming the amorphoussilicon region 10 to the above step effected should not be performed ata high temperature. This is because tho amorphous silicon region 10 atthe corner portion which is lying an region (boundary region) definedbetween the upper-end corner portion of the side wall of the elementisolating groove 4 and the end portion of the element forming regionformed in contact therewith may be spoiled due to such a process at ahigh temperature. In order to serve the above purpose, it is preferableto dope ion of an element such as oxygen or nitrogen which makessolid-phase growth speed low, so as to form the amorphous silicon region10.

[0123] Next, as shown in FIG. 7F, an underlying silicon nitride film(not shown) is formed on the exposed surface of the silicon substrate 1in the element forming region by the nitriding method with a nitrogenradical, NH₃ gas or NO gas, for example, a silicon nitride film (gateinsulating film) 8 a of 5 nm thickness is formed on the underlyingsilicon nitride film by use of the LPCVD method with a mixed gas of NH₃and SiH₂Cl₂.

[0124] In this case, if the underlying silicon nitride film is formedsuch that the thickness thereof on the central flat portion of thesilicon substrate 1 in the element forming region is approx. 1 nm, theunderlying silicon nitride film with a thickness of approx. 2 nm isformed at the corner portion which is a portion lying between theupper-end corner portion of the side wall of the element isolationgroove 4 and the end portion of the element forming region formed incontact therewith. The reason why the film thickness on the cornerportion becomes larger is that the amorphous silicon region 10 has beenformed in this portion and thus nitriding reaction may easily be causedtherein.

[0125] Therefore, as shown in FIG. 7G, the total thickness (5 nm) of theunderlying silicon nitride film (1 nm) and the gate insulating film(silicon nitride film) 8 (4 nm) on the central flat portion of thesilicon substrate 1 in the element forming region is smaller than thetotal thickness (6 nm) of the underlying silicon nitride film (2 nm) andthe gate insulating film (silicon nitride film) 6 (4 nm) at the cornerportion in the boundary region.

[0126] That is, according to this embodiment, the gate insulating film(silicon nitride film 8+underlying silicon nitride film) of which thefilm thickness on the surface of the silicon substrate 1 at the cornerportion is larger than the film thickness on the surface of the centralflat portion of the silicon substrate 1 in the element forming regioncan be formed in a self-alignment manner.

[0127] Next, as shown in FIG. 7F, an amorphous silicon film 9 with athickness of 100 nm which contains boron as impurity with high impurityconcentration and which will be used as a gate electrode is formed byuse of the LPCVD method.

[0128] After this, similar to a conventional MOS transistormanufacturing method, the processes for patterning the gate electrode,forming source and drain diffusion layers and forming wirings areeffected to complete the MOS transistor.

[0129] As described above, according to this embodiment, the siliconnitride film (gate insulating film) 8 having a large film thickness atthe corner portion in the boundary region can be formed in aself-alignment manner by nitriding the surface of the silicon substrateafter the corner portion is formed into an amorphous form withoutchanging the central flat portion of the silicon substrate 1 in theelement forming region into an amorphous form, and as a result, anincrease in the number of steps (time for effecting the steps) can beavoided. In addition, the same effect as that of the first embodimentcan be attained. Further, the same modification as that of the thirdembodiment can be applied to this embodiment.

[0130] This invention is not limited to the above embodiments. Forexample, in the above embodiments, a case wherein STI is used as theelement isolation technique is explained, but this invention iseffective when LOCOS is used as the element isolation technique.

[0131] In a case where LOCOS is used, since the silicon oxide film(element isolation film) 2 on the end portion of the element isolationregion formed in contact with the element forming region is removed whena cap silicon oxide film under the silicon nitride film is removed asshown in FIG. 8, the same problem as that occurring in the case of STIoccurs if the gate insulating film is formed in this state, but theproblem does not occur if the gate insulating film is formed accordingto this invention.

[0132] Further, though the above-described embodiments are explained inrelation to a MOS transistor, this invention also is applicable to a MIStype capacitor element. That is, a highly reliable MIS type capacitorelement, in which a lowering in the breakdown voltage in the cornerportion is suppressed, can be attained by omitting the source and draindiffusion layers from the MOS transistor in each of the aboveembodiments.

[0133] Further, this invention can be variously modified withoutdeparting from the technical scope thereof.

[0134] As described above, according to this invention, since a gateinsulating film (a silicon nitride film, a silicon oxide film containingnitrogen or a laminated film including the above films) in which thefilm thickness on the boundary region defined between the elementforming region and the element isolating region is larger than the filmthickness in a region of the element forming region can be formed in aself-alignment manner, a lowering in the breakdown voltage of the gateinsulating film in the boundary region between the element formingregion and the element isolating region can be suppressed withoutcausing an increase in the number of steps (time for effecting thesteps) and the manufacturing cost.

[0135] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

1. A semiconductor device comprising: a silicon substrate including anelement forming region, an element isolating region, and a boundaryregion including the boundary between the element forming region and theelement isolating region; and a gate insulating film formed on thesurface of the silicon substrate to extend from the element formingregion to the element isolating region across the boundary region,wherein the gate insulating film includes either of a silicon nitridefilm or a silicon oxide film containing nitrogen and is formed in aself-alignment manner to make the thickness of the gate insulating filmon the boundary region greater than the thickness of the gate insulatingfilm in the regions other than the boundary region.
 2. The semiconductordevice according to claim 1, wherein said gate insulating film is oflaminated structure including said silicon nitride film.
 3. A method formanufacturing a semiconductor device according to claim 1, comprisingthe steps of: dividing said silicon substrate into said element formingregion and said element isolating region; doping nitrogen into thesurface of said silicon substrate in said element forming region; andforming said gate insulating film on the surface of said siliconsubstrate so that said gate insulating film can extend from said elementforming region to said element isolating region across said boundaryregion, by the heat treatment in an atmosphere containing an oxidizingagent.
 4. The method according to claim 3, wherein: said step ofdividing said silicon substrate into said element forming region andsaid element isolating region is conducted by forming an elementisolating groove in the surface of said silicon substrate, said step ofdoping nitrogen into the surface of said silicon substrate in saidelement forming region comprises the steps of: filling an elementisolation insulatingfilm into the internal portion of the elementisolating groove to cover said silicon substrate at the upper-end cornerportion of the side wall formed by said element isolating groove;selectively doping nitrogen into the surface of the silicon substrate ina portion of the element forming region by using the element isolationinsulating film as a mask, and said step of forming said gate insulatingfilm further comprises a step of removing a portion of said elementisolation insulating film lying outside said element isolating groove sothat the upper-end corner portion of the side wall can be exposed. 5.The method according to claim 4, wherein a film of laminated structurehaving a nitrided silicon oxide film is used as said gate insulatingfilm in said step of forming the gate insulating film.
 6. The methodaccording to claim 4, wherein radical nitrogen is used for the doping ofnitrogen in said step of selectively doping nitrogen.
 7. The methodaccording to claim 4, wherein the doping of nitrogen is conducted byusing an ion-implantation method.
 8. A method for manufacturing thesemiconductor device according to claim 1, comprising the steps of:dividing a silicon substrate into an element forming region and anelement isolating region; doping nitrogen into the surface of thesilicon substrate in said boundary region; and forming a silicon nitridefilm or a silicon oxide film containing nitrogen as said gate insulatingfilm so that said gate insulating film can extend on the surface of saidsilicon substrate from the element forming region to said elementisolating region across said boundary region.
 9. The method according toclaim 8, wherein a deposition method is applied to said step of formingsaid silicon nitride film or said silicon oxide film containing nitrogenas said gate insulating film.
 10. The method according to claim 8,wherein a nitriding method is applied to said step of forming saidsilicon nitride film or said silicon oxide film containing nitrogen assaid gate insulating film.
 11. The method according to claim 8, themethod further comprising the step of forming an underlying siliconnitride film on the surface of said silicon substrate by using anitriding method prior to the formation of said silicon nitride film orsaid silicon oxide film containing nitrogen as said gate insulatingfilm, so that the underlying silicon nitride film can extend from saidelement forming region to said element isolating region across saidboundary region.
 12. The method according to claim 8, wherein: said stepof dividing said silicon substrate into said element forming region andsaid element isolating region is implemented by forming a mask patternon a silicon substrate and etching the silicon substrate with the maskpattern used as a mask to form an element isolating groove in thesurface of the silicon substrate.
 13. The method according to claim 12,wherein a deposition method is used in forming said silicon nitride filmor said silicon oxide film containing nitrogen as said gate insulatingfilm.
 14. The method according to claim 12, wherein a nitriding methodis used in forming said silicon nitride film or said silicon oxide filmcontaining nitrogen as said gate insulating film.
 15. The methodaccording to claim 12, wherein said gate insulating film is of laminatedstructure containing Ta₂O₅.
 16. A method for manufacturing thesemiconductor device according to claim 1, wherein: said siliconsubstrate is a crystalline silicon substrate, and the method comprisesthe steps of: dividing the crystalline silicon substrate into an elementforming region and an element isolating region; selectively forming thesurface of the silicon substrate in said boundary region into anamorphous form; and forming said silicon nitride film or said siliconoxide film containing nitrogen as said gate insulating film by use of anitriding method, so that said gate insulating film can extend from saidelement forming region to said element isolating region across saidboundary region.
 17. The method according to claim 16, furthercomprising the step of forming an underlying silicon nitride film on thesurface of said silicon substrate by using a nitriding method, prior tothe formation of said silicon nitride film or said silicon oxide filmcontaining nitrogen as said gate insulating film, so that the underlyingsilicon nitride film can extend from said element forming region to saidelement isolating region across said boundary region.
 18. The methodaccording to claim 16, wherein: said step of dividing said crystallinesilicon substrate into said element forming region and said elementisolating region comprises the steps of; forming a mask pattern on saidcrystalline silicon substrate; and etching said crystalline siliconsubstrate with the mask pattern used as a mask to form an elementisolating groove in the surface of said crystalline silicon substrate,said step of selectively forming the surface of the silicon substrate insaid boundary region into an amorphous form comprises the steps of:removing an end portion of the mask pattern which is formed in contactwith the upper-end corner portion of the side wall of the elementisolating groove; and implanting ions into the surface of the siliconsubstrate with the remaining portion of the mask pattern used as a maskto selectively form the surface of the silicon substrate into anamorphous form, and said step of forming said silicon nitride film orsaid silicon oxide film containing nitrogen as said gate insulating filmis carried out after the removal of the remaining portion of the maskpattern.
 19. The method according to claim 16, wherein a depositionmethod is applied to said step of forming said silicon nitride film orsaid silicon oxide film containing nitrogen as said gate insulatingfilm.
 20. The method according to claim 16, wherein a nitriding methodis applied to said step of forming said silicon nitride film or saidsilicon oxide film containing nitrogen as said gate insulating film.